Features

Target application

● Power meters

Ultra-low power consumption technology

● V DD = single power supply voltage of 1.7 to 5.5 V Note 1

● HALT mode

● STOP mode

● SNOOZE mode

RL78 CPU core

● CISC architecture with 3-stage pipeline

● Minimum instruction execution time: Can be changed from high speed (0.03125 µs: @ 32 MHz selection with PLL

clock, 0.04167 µs: @ 24 MHz selection with high-speed on-chip oscillator) to ultra-low speed (66.6 µs: @ 15 kHz

operation with low-speed on-chip oscillator)

● 16-bit multiplication, 16-bit multiply-accumulation, and 32-bit division are supported.

● Address space: 1 MB

● General-purpose registers: (8-bit register × 8) × 4 banks

● On-chip RAM: 6 KB to 16 KB

Code flash memory

● Code flash memory: 64 KB to 256 KB

● Block size: 1 KB

● Prohibition of block erase and rewriting (security function)

● On-chip debug function

● Self-programming (with boot swap function/flash shield window function)

Data flash memory

● Data flash memory: 2 KB

● Back ground operation (BGO): Instructions can be executed from the program memory while rewriting the data flash

memory

● Number of rewrites: 1,000,000 times (TYP.)

● Voltage of rewrites: V DD = 1.9 to 5.5 V

PLL clock Note 2

● 32 MHz is selectable (ΔΣ A/D converter is operable even when the PLL clock is selected as a CPU clock.)

High-speed on-chip oscillator

● Select from 1 to 24 MHz (TYP.). However when it is used as a clock for the ΔΣ A/D converter, select from 24 MHz

(TYP.), 12 MHz (TYP.), 6 MHz (TYP.), or 3 MHz (TYP.).

● High accuracy: ±1.0% (V DD = 1.9 to 5.5 V, T A = –20 to +85°C)