32-bit RX CPU core • Max. operating frequency: 32 MHz Capable of 50 DMIPS in operation at 32 MHz • Accumulator handles 64-bit results (for a single instruction) from 32-bit × 32-bit operations • Multiplication and division unit handles 32-bit × 32-bit operations (multiplication instructions take one CPU clock cycle) • Fast interrupt • CISC Harvard architecture with 5-stage pipeline • Variable-length instructions, ultra-compact code • On-chip debugging circuit